To understand how the architecture generated by fpgaConvNet as well as the optimisation steps taken, an interactive visualisation of the design space exploration is displayed below. By moving the interactive slide bar, the state of the optimised design can be seen. The performance graph shows the change in performance in throughput and latency across the optimisers steps, with the current visualised point highlighted. Likewise, the resources and block diagram for the chosen point are also shown. This visualisation is created for the model LeNet targeting a ZedBoard.