The results presented in this table are from our submission to MLPerf Tiny's benchmark, as part of the round v1.1 results. The MLPerf Tiny v1.1 submission demonstrates the versatility of the fpgaConvNet toolflow by targeting a range of low-cost FPGAs, whilst achieving ultra low latency across these devices. The obtained high performance is due to the exploration of the reconfigurability feature of FPGAs, allowing the tool to create highly tailored accelerator designs for each specific task and device. fpgaConvNet showcases the potential of FPGA devices for TinyML applications, as performance similar to that of ASICs is achieved whilst having the programmability of MCUs.
| Device | Task | Latency | LUT | DSP | BRAM | Freq. | |
|---|---|---|---|---|---|---|---|
| ZC706 | Image Classification | 0.15 ms | 108K | 564 | 281 | 187 MHz | link |
| Visual Wake Word | 0.72 ms | 133K | 564 | 366 | 200 MHz | link | |
| ZedBoard | Image Classification | 0.41 ms | 47K | 211 | 93 | 143 MHz | link |
| Visual Wake Word | 9.49 ms | 34K | 189 | 123 | 111 MHz | link | |
| Keyword Spotting | 0.32 ms | 37K | 188 | 97 | 143 MHz | link | |
| ZyBo | Image Classification | 3.15 ms | 16K | 78 | 36 | 125 MHz | link |
| Keyword Spotting | 2.15 ms | 15K | 60 | 16 | 125 MHz | link | |
| Cora-Z7 | Keyword Spotting | 4.21 ms | 13K | 55 | 28 | 143 MHz | link |
Instructions on how to use the bitstream can be found in the MLPerf-Tiny repo.
The results presented in this table are from our recently published research papers.